SIMD Programming with Larrabee: A Second Look at the Larrabee New Instructions (LRBni) in Action

Intel Japan K.K.
Friday, 18 December | 10:45 AM - 12:30 PM | Exhibition Hall B, Tech Talks Room 1

Larrabee is Intel's revolutionary approach to extending the evolving programmability of the GPGPU to its logical end. The Larrabee architecture features many cores and threads, as well as a new vector instruction-set extension (the Larrabee new instructions - LRBni). 
 
This talk examines the programming methods and hardware instructions that help programmers get the most out of LRBni's extremely wide vector units. Starting with simple math examples that are fairly simple to vectorize, it moves through loops, conditionals, and more complex flow control, showing how to implement these algorithms in LRBni. Next, the numerous choices of data format are examined: when to use SOA or AOS (and what those terms mean!), and how to use gather/scatter most efficiently from the same data structures used in an existing engine. The talk concludes with a quick look at efficient code scheduling and how to use the multiple hardware threads to help absorb instruction latencies.

Learning Objective
Understanding the latest processor architecture from Intel and the instruction set used to program it. This knowledge enables attendee to design the next iteration of their game engines and explore the possibilities available when programming Larrabee natively.
 

Intended Audience and Prerequisites
This talk is designed for programmers, although it will be interesting to anyone interested in Larrabee and why processor architecture is evolving in Larrabee's direction.

Intel Japan K.K.